Phase-locked loops are widely used for various applications such as in digital electronics, signal telemetry, and communications applications. A typical PLL may include a phase-frequency detector, a charge pump, and a voltage-controlled oscillator.
Phase-locked loop integrated circuits receive an input frequency signal and produce an oscillator frequency output signal. The frequency of the oscillator output signal may be a multiple of the frequency of the input signal. The PLL is said to be locked when the PLL produces an oscillator output signal which has a frequency which is a multiple of the input frequency signal within some tolerance. It is noted that a multiple of one is possible. Some applications using PLL circuits may use information regarding PLL lock. Useful information may include whether the PLL circuit is locked and when the lock is achieved.
There are devices and methods for determining PLL lock within the prior art. However, some such devices and methods may at times incorrectly indicate that a PLL has achieved lock. Accordingly, it is desirable to configure PLL circuits such that PLL lock may be determined more reliably. In addition, such prior art locking devices and methods may require complicated circuitry to enable, and these complicated circuits may have large footprints. It is desirable to reduce the footprint of the PLL and its related circuitry. This is particularly true when considering PLL circuits manufactured using CMOS technologies. Thus, it is desirable to determine PLL lock using relatively simple circuitry which may have a reduced footprint size.